Introduction to logic synthesis using Verilog HDL / Robert B. Reese, Mitchell A. Thornton.
- 其他題名：
- San Rafael, Calif. (1537 Fourth Street, San Rafael, CA 94901 USA) :
- Synthesis digital library of engineering and computer science.
- 出版： Morgan & Claypool Publishers c2006.
- 叢書名： Synthesis lectures on digital circuits and systems, ;#6
- 主題： Logic design. , Verilog (Computer hardware description language) , Electronic digital computers , Computer hardware description languages.
- URL：
電子書
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讀者標籤：
- 系統號： 005151364 | 機讀編目格式
館藏資訊
內容註
Digital logic review with Verilog quickstart -- Learning objectives -- Logic synthesis introduction and motivation -- Combinational logic in Verilog -- Assign statements -- Always procedural blocks -- Combinational building blocks in Verilog -- Multibit/multiinput muxes, Verilog hierarchical design and bus notation -- Addition, subtraction -- Multiplication, division -- Shifting -- Tri-state logic -- Sequential logic in Verilog -- One-bit storage elements -- DFF chains -- Asynchronous versus synchronous inputs -- Registers, counters, and shift registers -- Event-driven simulation and Verilog -- Event-driven simulation basics -- Timing considerations -- Presynthesis versus postsynthesis simulation -- Blocking versus nonblocking assignments and synthesis -- Verilog coding guidelines -- Summary -- Synchronous sequential circuit design -- Learning objectives -- Sequential circuits -- Sequential circuit motivation -- Synchronizing signals: the clock -- Synchronous sequential circuit architectures -- Contents -- Models of finite state machines -- Basics of algorithmic state machine (ASM) charts -- The ASM chart model and an example controller -- The state diagram model -- State assignment -- Low-level models of controllers -- State equations -- State tables -- Controller circuit analysis -- Mealy and Moore machine conversion -- Mealy to Moore machine conversion -- Moore to Mealy conversion -- State machine equivalence -- Verilog descriptions of synchronous sequential circuits -- Example Verilog descriptions -- Verilog descriptions for the Mealy machine model of an example controller -- Verilog descriptions for the Moore machine model of an example controller -- Summary -- Biography.