Introduction to Logic Synthesis using Verilog HDL [electronic resource] / by Robert B. Reese, Mitchell A. Thornton.
- 作者: Reese, Robert B. author.
- 其他作者:
- 其他題名:
- Synthesis Lectures on Digital Circuits & Systems,
- 出版: Cham : Springer International Publishing :Imprint: Springer 2006.
- 叢書名: Synthesis Lectures on Digital Circuits & Systems,
- 主題: Engineering. , Electronic circuits. , Control engineering. , Robotics. , Automation. , Computers. , Technology and Engineering. , Electronic Circuits and Systems. , Control, Robotics, Automation. , Computer Hardware.
- 版本:1st ed. 2006.
- ISBN: 9783031797439
- URL:
Electronic resource
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讀者標籤:
- 系統號: 005282043 | 機讀編目格式
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摘要註
Introduction to Logic Synthesis Using Verilog HDL explains how to write accurate Verilog descriptions of digital systems that can be synthesized into digital system netlists with desirable characteristics. The book contains numerous Verilog examples that begin with simple combinational networks and progress to synchronous sequential logic systems. Common pitfalls in the development of synthesizable Verilog HDL are also discussed along with methods for avoiding them. The target audience is anyone with a basic understanding of digital logic principles who wishes to learn how to model digital systems in the Verilog HDL in a manner that also allows for automatic synthesis. A wide range of readers, from hobbyists and undergraduate students to seasoned professionals, will find this a compelling and approachable work. The book provides concise coverage of the material and includes many examples, enabling readers to quickly generate high-quality synthesizable Verilog models.