Finite State Machine Datapath Design, Optimization, and Implementation [electronic resource] / by Justin Davis, Robert Reese.
- 作者: Davis, Justin. author.
- 其他作者:
- 其他題名:
- Synthesis Lectures on Digital Circuits & Systems,
- 出版: Cham : Springer International Publishing :Imprint: Springer 2008.
- 叢書名: Synthesis Lectures on Digital Circuits & Systems,
- 主題: Engineering. , Electronic circuits. , Control engineering. , Robotics. , Automation. , Computers. , Technology and Engineering. , Electronic Circuits and Systems. , Control, Robotics, Automation. , Computer Hardware.
- 版本:1st ed. 2008.
- ISBN: 9783031797767
- URL:
Electronic resource
-
讀者標籤:
- 系統號: 005282095 | 機讀編目格式
館藏資訊
Finite State Machine Datapath Design, Optimization, and Implementation explores the design space of combined FSM/Datapath implementations. The lecture starts by examining performance issues in digital systems such as clock skew and its effect on setup and hold time constraints, and the use of pipelining for increasing system clock frequency. This is followed by definitions for latency and throughput, with associated resource tradeoffs explored in detail through the use of dataflow graphs and scheduling tables applied to examples taken from digital signal processing applications. Also, design issues relating to functionality, interfacing, and performance for different types of memories commonly found in ASICs and FPGAs such as FIFOs, single-ports, and dual-ports are examined. Selected design examples are presented in implementation-neutral Verilog code and block diagrams, with associated design files available as downloads for both Altera Quartus and Xilinx Virtex FPGA platforms. A working knowledge of Verilog, logic synthesis, and basic digital design techniques is required. This lecture is suitable as a companion to the synthesis lecture titled Introduction to Logic Synthesis using Verilog HDL. Table of Contents: Calculating Maximum Clock Frequency / Improving Design Performance / Finite State Machine with Datapath (FSMD) Design / Embedded Memory Usage in Finite State Machine with Datapath (FSMD) Designs
摘要註
Finite State Machine Datapath Design, Optimization, and Implementation explores the design space of combined FSM/Datapath implementations. The lecture starts by examining performance issues in digital systems such as clock skew and its effect on setup and hold time constraints, and the use of pipelining for increasing system clock frequency. This is followed by definitions for latency and throughput, with associated resource tradeoffs explored in detail through the use of dataflow graphs and scheduling tables applied to examples taken from digital signal processing applications. Also, design issues relating to functionality, interfacing, and performance for different types of memories commonly found in ASICs and FPGAs such as FIFOs, single-ports, and dual-ports are examined. Selected design examples are presented in implementation-neutral Verilog code and block diagrams, with associated design files available as downloads for both Altera Quartus and Xilinx Virtex FPGA platforms. A working knowledge of Verilog, logic synthesis, and basic digital design techniques is required. This lecture is suitable as a companion to the synthesis lecture titled Introduction to Logic Synthesis using Verilog HDL. Table of Contents: Calculating Maximum Clock Frequency / Improving Design Performance / Finite State Machine with Datapath (FSMD) Design / Embedded Memory Usage in Finite State Machine with Datapath (FSMD) Designs.
內容註
Calculating Maximum Clock Frequency -- Improving Design Performance -- Finite State Machine with Datapath (FSMD) Design -- Embedded Memory Usage in Finite State Machine with Datapath (FSMD) Designs.